1. Field of the Invention
The invention relates to a sampling-error phase compensating device and a method thereof, and more particularly to a sampling-error phase compensating device and a method thereof, both of which are applied to a data recovery system.
2. Description of the Related Art
In a data recovery system, a sampling circuit is needed to sample data signals. FIGS. 1A to 1D are schematic illustrations showing the operation principle for a sampling circuit. As shown in FIGS. 1A to 1D, the data signals are a series of continuous signals with specific working frequency, and the sampling circuit samples the data signals at sampling points according to a sampling clock signal. When the sampling point is positioned at a middle portion in each segment of the data signal, as shown at the sampling point P1 of FIG. 1A, the sampling error of the sampled data signal obtained by the sampling of the sampling circuit tend to be small. However, if the sampling point is not positioned at the middle portion in each segment of the data signal but at a transition portion, as shown at the sampling point P2 of FIG. 1B, the sampled data signal obtained by the sampling of the sampling circuit may induce serious sampling error because the signal value of the data signal at the transition portion is not stable. When the sampling point is at the front portion in each period of the data signal, as shown in FIG. 1C, it is termed “phase leading” of the sampling point. When the sampling point is at the rear portion in each period of the data signal, as shown in FIG. 1D, it is termed “phase lagging” of the sampling point. The position (i.e., phase) of each sampling point in the data signal may influence the sampling error of the sampled signal, and thus cause great influence on the operation of the data recovery system. Consequently, how to decrease the sampling error in the data recovery system is a very important subject.
The typical sampling circuits applied to the data recovery system may be divided into two categories, which are feedforward sampling circuits and feedback sampling circuits. The operation principle of the feedforward sampling circuit is to utilize an over-sampling unit to over-sample the input data signals. That is, each data signal is sampled for multiple times. Then, a phase regulator selects correctly sampled data signals for output according to the magnitudes of multiple over-sampled data signals corresponding to each data signal. However, the feedforward sampling circuit is not suitable for the data recovery system having data signals with high working frequency because the sampling frequency of the over-sampling circuit is far higher than the working frequency of the data signal.
FIG. 2 is a schematic illustration showing a conventional feedback sampling circuit. The conventional feedback sampling circuit 200 typically utilizes a phase detector 210 and a phase regulator 230. In addition to performing the function of sampling on the data signal, the phase detector 210 detects the phase of the sampling point imposed by a sampling clock signal at each period of the data signal so as to output a phase detection signal. Then the phase regulator 230 adjusts the sampling clock signal of the phase detector 210 according to the phase detection signal, usually filtered by a digital loop filter 220, such that the phase leading or phase lagging of the sampling points causing sampling error can be properly adjusted.
However, due to time delay from detection of phase error to adjustment of sampling clock signal inherent in electronic circuits, the feedback sampling circuit tends to over-adjust the sampling clock signal. This results in a relatively large swing range of the magnitude of phase errors, and therefore may induce even more serious sampling error.
FIG. 3 is a schematic illustration showing the operation of the conventional feedback sampling circuit. As shown in FIG. 3, the phase detection, phase regulation and sampling clock on the horizontal axis represent output signals of the phase detector, the digital loop filter and the phase regulator in the feedback sampling circuit, respectively, wherein “+” represents that the signal is to regulate the sampling point forward on the phase of the data signal, and “−” represents that the signal is to regulate the sampling point backward on the phase of the data signal. The phase error represents the extent of the error of the sampling point on the phase of the data signal, wherein “+” represents the phase leading and “−” represents the phase lagging. The conventional feedback sampling circuit of FIG. 2 is a pipeline circuit. When the phase detector detects the phase of the sampling point lags behind 0.5 units at time T0, the phase regulator will not correspondingly regulate the phase of the sampling clock signal according to the phase error after three units of time have been elapsed (i.e., at time T3). The pipeline circuit structure of the feedback sampling circuit causes the time delay from the time when the phase detector detects the phase error to another time when the phase regulator regulates the sampling clock signal according to the phase error. The length of the delay time is determined by the circuit architecture of the conventional feedback sampling circuit. The more the number of circuit components of the pipeline circuit is, the longer the delay time is. This is one of the drawbacks of the conventional feedback sampling circuit. In the above-mentioned, conventional feedback sampling circuit, the delay time k=3. However, in the practical data recovery system, the problem of the time delay is more serious than that in the circuit of FIG. 2, and thus k is usually greater than 3. In addition, when the phase detector detects the phase error at time T0, the phase regulator will not regulate the phase of the sampling clock signal according to the phase error after three units of time have been elapsed (i.e., at time T3). So, the phase detection signal is kept at “+” at time T2 and T3, and these “+” signals regulate the sampling clock at time T4 and T5, respectively. That is, since the drawback of time delay exists in the conventional feedback sampling circuit having the pipeline circuit structure as shown in FIG. 2, the feedback circuit continuously over-regulates the phase of the sampling clock signal as long as the phase error, regardless of its magnitude, does exist. In this context, the phenomenon is referred to as the accumulative regulation. Even if the initial phase error is smaller than one unit (−0.5), the circuit of FIG. 2 continuously regulates the phase of the sampling clock signal at least three times, thereby causing the magnitude of the phase error of the conventional feedback sampling circuit to swing between a large range (+3.5 to −2.5), as shown in FIG. 4. Consequently, the conventional feedback sampling circuit may even cause more serious sampling errors during its sampling-error phase regulation process. In particular, if the delay time is too long, the magnitude of the phase error may be caused to diverge, and thus the compensation cannot be made.
Thus, it is necessary to overcome the drawback in the conventional phase detection system.